Freescale Semiconductor /MK60DZ10 /MCG /C6

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Interpret as C6

7 43 0 0 00 0 0 0 0 0 0 0 0VDIV0 (0)CME 0 (0)PLLS 0 (0)LOLIE

PLLS=0, LOLIE=0, CME=0

Description

MCG Control 6 Register

Fields

VDIV

VCO Divider

CME

Clock Monitor Enable

0 (0): External clock monitor is disabled.

1 (1): Generate a reset request on loss of external clock.

PLLS

PLL Select

0 (0): FLL is selected.

1 (1): PLL is selected (PRDIV need to be programmed to the correct divider to generate a PLL reference clock in the range of 2 - 4 MHz prior to setting the PLLS bit).

LOLIE

Loss of Lock Interrrupt Enable

0 (0): No interrupt request is generated on loss of lock.

1 (1): Generate an interrupt request on loss of lock.

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